The present invention relates to an ion beam etching method and an ion beam etching apparatus, and more particularly to a method of and an apparatus for etching semiconductor devices such a very large scale integration circuit by a ion beam.
An ion beam etching apparatus is disclosed in U.S. Pat. Nos. 4,503,329, 4,609,809 and 4,683,378. That is, the ion beam etching apparatus is used as a mask repair apparatus or wafer repair apparatus. According to an ordinary ion beam etching method, an ion beam performs a scanning operation at a rectangular area, to etch a region having the form of a rectangular parallel piped. Further, an example of two-stage ion beam etching is shown in FIG. 1 of an article entitled "Focused Ion Beam Microsurgery for Electronics" by C. R. Musil (IEEE ELECTRON DEVICE LETTERS EDL7, 5, MAY, 1986). In this example, upper and lower wiring conductors are connected to each other by a focused ion beam. That is, the above example has no connection with means for preventing the shorting between the upper and lower wiring conductors due to ion beam etching.
According to the conventional ion beam etching method, when a hole is made in a semiconductor device by an ion beam to expose a lower wiring conductor, there is a fear that the lower wiring conductor is shorted to an upper wiring conductor, and thus the manufacturing yield in wiring process is reduced.
Further, an example, of the etching of a large scale integration circuit by a focused ion beam is described on pages 176 through 180 of the J. Vac. Sci. Techno., B4 (1), Jan/Feb, 1989. As shown in this example, when a specimen surface having a step-like portion is etched by a focused ion beam, the etching operation is affected by the step-like portion, and the bottom of a hole made by the ion beam etching is inclined or has unevenness. The inclination and unevenness of the bottom reduce the margin of etching depth, and lower the manufacturing yield in etching process.